JPH0141034B2 - - Google Patents
Info
- Publication number
- JPH0141034B2 JPH0141034B2 JP20865982A JP20865982A JPH0141034B2 JP H0141034 B2 JPH0141034 B2 JP H0141034B2 JP 20865982 A JP20865982 A JP 20865982A JP 20865982 A JP20865982 A JP 20865982A JP H0141034 B2 JPH0141034 B2 JP H0141034B2
- Authority
- JP
- Japan
- Prior art keywords
- plating
- lead frame
- metal strip
- lead
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007747 plating Methods 0.000 claims description 50
- 239000002184 metal Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000010970 precious metal Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 7
- 238000004080 punching Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000002950 deficient Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20865982A JPS5999750A (ja) | 1982-11-30 | 1982-11-30 | Ｉｃ用リ−ドフレ−ムの製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20865982A JPS5999750A (ja) | 1982-11-30 | 1982-11-30 | Ｉｃ用リ−ドフレ−ムの製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5999750A JPS5999750A (ja) | 1984-06-08 |
| JPH0141034B2 true JPH0141034B2 (en]) | 1989-09-01 |
Family
ID=16559912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20865982A Granted JPS5999750A (ja) | 1982-11-30 | 1982-11-30 | Ｉｃ用リ−ドフレ−ムの製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5999750A (en]) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59188952A (ja) * | 1983-04-11 | 1984-10-26 | Shinko Electric Ind Co Ltd | リ−ドフレ−ムの製造方法 |
| US5742009A (en) * | 1995-10-12 | 1998-04-21 | Vlsi Technology Corporation | Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microeletronics packages via condution through the package leads |
-
1982
- 1982-11-30 JP JP20865982A patent/JPS5999750A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5999750A (ja) | 1984-06-08 |
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